The design of modern integrated circuits can be significantly constrained by interconnect signal propagation delays. Signal propagation delays arise due to the resistance and capacitive coupling of interconnects connecting different parts (e.g. functional blocks) of a chip, and are commonly called RC delays. RC effects can also affect the amplitude or waveshape of the transmitted signals. Addressing RC effects is becoming increasingly important as the gate counts, clock speeds and chip sizes of integrated circuits continue to grow.
Signal repeaters such as buffers or inverters can be inserted in the signal paths between different functional blocks physically situated on distant parts of a chip. Since propagation delays typically increase non-linearly (e.g. quadratically) with signal path length, inserting such repeaters reduces the time required for signals to travel between the functional blocks. Nevertheless, as chip sizes and clock speeds increase, such signal repeaters may not be adequate for meeting timing constraints imposed by functional block communications protocols. Redesigning such communications protocols and/or chip layouts can add significant complexity, time, and cost to the design of integrated circuits. For information on integrated circuits and design methods employing signal repeaters see for example U.S. Pat. Nos. 6,473,889, 6,463,574, 6,449,769, 6,412,101, 6,408,426, 6,145,116, and 6,009,253.